Using VHDL for Board Level Simulation

encountered in ASIC (applicationspecific integrated circuit) developments originate from unclear or incorrectly implemented specifications. To allow independent evaluation of a device’s functionality, the European Space Agency (ESA) normally requests a VHDL model before a company starts the detailed design. This allows ESA or another company to verify the functionality. (For more about ESA and its choice of VHDL, see the box.) A logical follow-on activity to using VHDL modeling for ASIC design verification is to model and simulate complete board designs.